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This not only improves performance, but also allows the Southbridge to take advantage of the 28SHP process rather than older, more power-hungry 45nm or 65nm process nodes. In addition, the Excavator cores used in Carrizo have switched from a High Performance Library (HPL) to a High Density Library (HDL) design. This allows for a reduction in the die area taken up by the processing cores (23 percent, according to AMD). This allows Carrizo to pack in 29 percent more transistors (3.1 billion versus 2.3 billion in Kaveri) in a die size that is only marginally larger (250mm2 for Carrizo versus 245mm2 for Kaveri). When all is said and done, AMD is claiming a 5 percent IPC boost for Carrizo and a 40 percent overall reduction in power usage.